A storage controller generally controls data I/O (Input/Output). The storage controller manages a LU (Logical Unit) as a logical storage device. The storage controller receives from a host device an I/O command (either a write command or a read command) specifying a logical area (for example, the LU and an area inside the LU), and carries out the I/O of data with respect to this I/O command-specified logical area.
A device having a plurality of controllers (hereinafter, controller will be abbreviated as “CTL”), for example, a dual CTL is known as a storage controller. Each CTL in the dual CTL comprises owner rights of a LU and a cache area (hereinafter, CM area). Upon receiving an I/O command from the host device, in a case where the LU owner specified by this I/O command is itself, the CTL writes data (original data) that conforms to the I/O command to its own CM area, and, in addition, writes mirror data (a replication of the original data) to the CM area of the other CTL. That is, the cache mirroring is performed.
Patent Literature 1 discloses a technique for a cache-mirroring write-confirm method, which uses PCI-Express as the interconnector between the CTLs, and utilizes DMA (Direct Memory Access). Hereinbelow, the storage controller is assumed to be a dual CTL, and in a case where the dual CTL processes a command, the CTL, which processes the command, will be called an “own-system CTL”, and the CTL, which does not process the command, will be called an “other-system CTL”.
In order to carry out cache mirroring from the own-system CTL to the other-system CTL, it is necessary to access the cache memory of the other-system CTL, which is the mirroring destination. However, because cache memory is managed separately in each CTL, for the own-system CTL to access the cache memory of the other-system CTL, it is necessary to reserve a write-destination area, to lock the resource for this area, and to manage the resource.
In order to simplify this processes, a method for reserving an area for storing mirror data (hereinafter, the mirror area) beforehand inside the cache memory of the other-system CTL, and managing this area in the mirror-source CTL (the own-system CTL) has been proposed (Patent Literature 2). In accordance with this, the lock-free control of the other-system cache becomes possible.
Meanwhile, to avoid the degradation of I/O performance resulting from the cache mirroring process, performing this processing via high-speed dedicated hardware is conceivable, and Patent Literature 3 discloses a technique for carrying out high-speed mirroring in accordance with cache control circuits connected by a dedicated bus.
Generally speaking, in a dual controller, the CTLs are most often symmetrical, and for this reason, the reciprocal CM areas are the same size and a mirroring technique that is premised on this fact is adopted. However, in recent years, there have been a number of cases in which this symmetry has broken down due to both hardware and software reasons. Hardware causes include cases in which the initial CM capacities simply differ, and cases in which the CM area fails during operation. The software causes include cases in which the CM capacity provided from the hypervisor in the host device (for example, the server) virtualization technology differs in the two CTLs.